View M440T1MV-15ZA9_1269625.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M440T1MV
3.3V, 32 Mbit (1024 Kbit x 32) TIMEKEEPER(R) SRAM
FEATURES SUMMARY

3.3V 10% INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY, AND CRYSTAL PRECISION POWER MONITORING AND POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION WHEN VCC IS OUT-OF-TOLERANCE POWER-FAIL DESELECT VOLTAGE: - VCC = 3.0 to 3.6V; 2.8V VPFD 2.97V BATTERY LOW PIN (BL) DUAL BATTERY SNAPHAT(R) HOUSING IS REPLACEABLE 85ns SRAM CHIP ENABLE ACCESS (70ns ADDRESS ACCESS) SLEEP MODE FUNCTION 150ns CLOCK ACCESS
Figure 1. Package
M440T1MV
168-ball PBGA Module
October 2004
1/26
M440T1MV
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Figure 5. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PBGA Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . M440T1MV Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . M440T1MV PBGA Module Solution (Side/Top). . . . . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....5 .....6 .....7
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Memory READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Clock READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Memory Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Clock Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Memory READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled . . . . . . 9 Figure 7. Memory READ Mode AC Waveforms, Address-Controlled . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. Clock READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled . . . . . . . 10 Figure 9. Clock READ Mode AC Waveforms, Address-Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Memory/Clock READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Memory WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10.Memory WRITE Mode AC Waveforms, WRITE Enable-Controlled . . . . . . . . . . . . . . . . 11 Figure 11.Memory WRITE Mode AC Waveforms, Chip Enable-Controlled . . . . . . . . . . . . . . . . . . 12 Figure 12.Clock WRITE Mode AC Waveforms, WRITE Enable-Controlled . . . . . . . . . . . . . . . . . . 12 Figure 13.Clock WRITE Mode AC Waveforms, Chip Enable-Controlled. . . . . . . . . . . . . . . . . . . . . 13 Table 5. Memory/Clock WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reading and Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock Alarm Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Watchdog Alarm Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Time of Day Alarm Mask Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Battery Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/26
M440T1MV
Table 9. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 14.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 13. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 16.PBGA-ZA - 168-ball Plastic Ball Grid Array Package Outline . . . . . . . . . . . . . . . . . . . . 22 Table 14. PBGA-ZA - 168-ball Plastic Ball Grid Array Package Mechanical Data . . . . . . . . . . . . . 23 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
M440T1MV
SUMMARY DESCRIPTION
The M440T1MV TIMEKEEPER(R) RAM is a 16Mbit, non-volatile static RAM organized as 1,024K by 32 bits and real time clock organized as 64 bytes by 8 bits. The special PBGA package provides a fully integrated battery back-up memory and real time clock solution. In the event of power instability or absence, a self-contained battery maintains the timekeeping operation and provides power for a CMOS static RAM. Control circuitry monitors VCC and invokes write protection to prevent data corruption in the memory and RTC. The clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with less than 31 days, including leap year correction. The clock operates in one of two formats: - a 12-hour mode with an AM/PM indicator; or - a 24-hour mode The M440T1MV is in a 168-ball PBGA module that integrates the RTC, the battery, and SRAM in one package.
Figure 2. Logic Diagram
Table 1. Signal Names
A0 - A19 DQ0 - DQ31 Address Inputs NVRAM Data Input/Output Clock Data Input/Output NVRAM Chip Enable Inputs Clock Chip Enable Input NVRAM WRITE Enable Inputs Clock WRITE Enable Input Output Enable Input Clock Output Enable Input Battery Low Output (Open Drain) Interrupt Output (Open Drain) Reserved Reserved No Connect Supply Voltage Ground
VCC
DQC0 - DQC7 E1 - E4
A0 - A19 DQ0 - DQ31 E1 - E4 DQC0 - DQC7 EC BL W1 - W4 WC RSV1 G RSV2 GC M440T1MV IRQ
EC W1 - W4 WC G GC BL IRQ RSV1 RSV2
VSS
AI04200
NC VCC VSS
4/26
M440T1MV
Figure 3. PBGA Connections (Top View)
80 79 62 61 74 73 72 71 70 69 68 67 63 78 77 76 75 66 65 64 60
A11 A8
A0 W4 A1
BL E1
VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
A15 A17 A13 A18 W1 A16 A14 A12 A7 A6 A5 DQ7 DQ6 DQ5 A19 DQ4 DQ0 DQ1 DQ2 M440T1MV
A4 VCC
G
A9
W2 E2
E4 A10
EC
WC
GC
A2 A3
E3 DQ31 DQ30 DQ29 W3 DQ28 DQ27 DQ24 DQ25 DQ26 DQ16 DQ17 DQ18 DQ23 RSV1 DQ22 DQ21 DQ20 DQ19
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
DQC3
DQC4
DQC5
DQC7
DQC0
DQC6
DQC1
DQC2 DQ10
DQ15
IRQ DQ14
DQ13 37
RSV2
DQ12 38
20 21
30 31
22 23
32
DQ9 DQ8
24 25
26
35
33
29
27
28
34
36
39 40
DQ11 VSS
DQ3
VSS
AI04794
Note: This diagram is TOP VIEW perspective (view through package).
5/26
M440T1MV
Figure 4. M440T1MV Hardware Hookup
DQ8-DQ15 G G G G
AI04795
DQ0-DQ7
A0-A19
20
20 VCC E
8
3.3V VCC 6 A0-A5
VOUTA
VCC 1M x 8 SRAM E1CON E2CON E G W
1M x 8 SRAM W
EC WC GC E1 E2 E3 E4 SLEEP PAD 8k VOUTA
E W G E1
DQ0 - DQ7 INTB/INTB
DQC0 - DQC7 IRQ
G
W1 DQ16-DQ23
BL E2 E3 E4 SLEEP
BL
20
20
8
VOUTB
VCC 1M x 8 SRAM E3CON E4CON G W3 E G W
VCC 1M x 8 SRAM E W
THS VSS
6/26
8 W4
DQ24-DQ31
A0-A19
A0-A19
8 W2
M48T224W
A0-A19
M440T1MV
Figure 5. M440T1MV PBGA Module Solution (Side/Top)
AI04628b
7/26
M440T1MV
OPERATION MODES
Memory READ Mode The M440T1MV is in the 32-bit READ Mode whenever W1 - W4 (WRITE Enable Byte 1 to 4) are high and E1 - E4 - Chip Enable Bytes 1 to 4 are low (see Table 2., page 8). The unique address specified by the 20 address inputs defines which one of the 1,048,576 long words of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access Time (tAVQV) after the last address input signal is stable, providing the E1-4 and G access times are also satisfied. If the E1-4 and G access times are not met, valid data will be available after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time (tGLQV). The state of the thirty-two three-state Data I/O signals is controlled by E1-4 and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E1-4 and G remain active, output data will remain valid for Output Data Hold Time (tAXQX) but will go indeterminate until the next Address Access. Table 2. Memory Operating Modes
Mode Byte WRITE Byte WRITE Byte WRITE Byte WRITE Byte WRITE Byte WRITE Byte WRITE Byte WRITE Long Word WRITE Byte READ Byte READ Byte READ Byte READ Long Word READ Deselect Deselect VSO to VPFD(min)(1) VSO(1) 2.97 to 3.6V L H H H L L H X L H H L H L H X L H L H H L H X L L H H H L H X H L L L L L X X L X X X H H X X L X X H X H X X L X H X X H X X L H X X X H X X DIN Hi-Z Hi-Z Hi-Z DOUT DOUT Hi-Z Hi-Z DIN Hi-Z Hi-Z DOUT Hi-Z DOUT Hi-Z Hi-Z DIN Hi-Z DOUT Hi-Z Hi-Z DOUT Hi-Z Hi-Z DIN DOUT Hi-Z Hi-Z Hi-Z DOUT Hi-Z Hi-Z Active Active Active Active Active Active Stdby CMOS Standby VCC E4 H H H L X X X L E3 H H L H X X L X E2 H L H H X L X X E1 L H H H L X X X G H H H H H H H H W4 X X X L H H H L W3 X X L X H H L H W2 X L X X H L H H W1 L X X X L H H H DQ24- DQ16- DQ8- DQ0DQ31 DQ23 DQ15 DQ7 Hi-Z Hi-Z Hi-Z DIN Hi-Z Hi-Z Hi-Z DIN Hi-Z Hi-Z DIN Hi-Z Hi-Z Hi-Z DIN Hi-Z Hi-Z DIN Hi-Z Hi-Z Hi-Z DIN Hi-Z Hi-Z DIN Hi-Z Hi-Z Hi-Z DIN Hi-Z Hi-Z Hi-Z Power Active Active Active Active Active Active Active Active
Clock READ Mode The clock is in the READ Mode whenever WC (Clock WRITE Enable) is high and EC (Clock Chip Enable) is low. The unique address specified by the 6 Address Inputs defines which one of the 64 bytes of clock data is to be accessed. Valid data will be available at the Data I/O pins (DQC0-7) within Address Access Time (tAVQV) after the last address input signal is stable, providing the EC and GC access times are also satisfied. If the EC and GC access times are not met, valid data will be available after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by EC and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while EC and G remain active, output data will remain valid for Output Data Hold Time (tAXQX) but will go indeterminate until the next Address Access. See section on Reading and Setting the Clock under CLOCK OPERATION for more details.
Deselect
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Battery Hi-Z Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 12., page 20 for details.
8/26
M440T1MV
Table 3. Clock Operating Modes
Mode Deselect WRITE 2.97 to 3.6V READ READ Deselect Deselect VSO to VPFD(min)(1) VSO(1) VIL VIL X X VIL VIH X X VIH VIH X X DOUT Hi-Z Hi-Z Hi-Z VCC EC VIH VIL GC X X WC X VIL DQC0 - 7 Hi-Z DIN
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 12., page 20 for details.
Figure 6. Memory READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled
tAVAV A0-A19 tAVQV tELQV E1 - E4 tELQX tGLQV G tGLQX DQ0-DQ31 DATA OUT
AI05606
VALID tAXQX tEHQZ
tGHQZ
Figure 7. Memory READ Mode AC Waveforms, Address-Controlled
tAVAV A0-A19 tAVQV tAXQX DQ0-DQ31 DATA VALID DATA VALID VALID
AI05607
9/26
M440T1MV
Figure 8. Clock READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled
tAVAV A0-A5 tAVQV tELQV EC tELQX tGLQV GC tGLQX DQC0-DQC7 DATA OUT
AI04653
VALID tAXQX tEHQZ
tGHQZ
Figure 9. Clock READ Mode AC Waveforms, Address-Controlled
tAVAV A0-A5 tAVQV tAXQX DQC0-DQC7 DATA VALID DATA VALID VALID
AI04654
Table 4. Memory/Clock READ Mode AC Characteristics
M440T1MV Symbol Parameter(1) Memory -85 Min tRC tACC tCO tOE tCEL tOEL tCEZ tOEZ tOH tAVAV tAVQV tELQV tGLQV tELQX tGLQX READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition 5 5 40 30 5 5 85 70 85 45 10 5 50 50 Max Min 150 150 150 70 Clock -15 Max ns ns ns ns ns ns ns ns ns Unit
tEHQZ(2) Chip Enable High to Output Hi-Z tGHQZ(2) Output Enable High to Output Hi-Z tAXQX Address Transition to Output Transition
Note: 1. Valid for Ambient Operating Temperature: TA = -15 to 75C; VCC = 3.0 to 3.6V (except where noted). 2. CL = 5pF.
10/26
M440T1MV
Memory WRITE Mode The M440T1MV is in the WRITE Mode whenever any or all of W1-4 (WRITE Enable Byte 1 to 4) and any corresponding E1-4 (Chip Enable Byte 1 to 4) are in a low state after the address inputs are stable. Thus a Byte WRITE (8-bit), Word WRITE (16bit) or Long Word WRITE (32-bit) may be performed. The start of a WRITE is referenced from the latter occurring falling edge of W1-4 or E1-4. A WRITE is terminated by the earlier rising edge of W1-4 or E1-4. The addresses must be held valid throughout the cycle. E1-4 or W1-4 must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E1-4 and G, a low on W1-4 will disable the outputs tWLQZ after W1-4 falls. Clock WRITE Mode The clock is in the WRITE Mode whenever WC (Clock WRITE Enable) and EC (Clock Chip Enable) are in the low state after the address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of WC or EC. A WRITE is terminated by the earlier rising edge of WC or EC. The addresses must be held valid throughout the cycle. EC or WC must return high for a minimum of tEHAX from Chip Enable Clock or tWHAX from WRITE Enable Clock prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. GC should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on EC and GC a low on WC will disable the outputs tWLQZ after WC falls. See section on Reading and Setting the Clock under CLOCK OPERATION for more details.
Figure 10. Memory WRITE Mode AC Waveforms, WRITE Enable-Controlled
tAVAV A0-A19 VALID tAVWH tAVEL E1 - E4 tWLWH tAVWL W1 - W4 tWLQZ tWHDX DQ0-DQ31 DATA INPUT tDVWH
AI05608
tWHAX
tWHQX
Note: Output Enable (G) = Low
11/26
M440T1MV
Figure 11. Memory WRITE Mode AC Waveforms, Chip Enable-Controlled
tAVAV A0-A19 VALID tAVEH tAVEL E1 - E4 tAVWL W1 - W4 tWHDX DQ0-DQ31 DATA INPUT tDVWH
AI05609
tELEH
tEHAX
Note: Output Enable (G) = High
Figure 12. Clock WRITE Mode AC Waveforms, WRITE Enable-Controlled
tAVAV A0-A5 VALID tAVWH tAVEL EC tWLWH tAVWL WC tWLQZ tWHDX DQC0-DQC7 DATA INPUT tDVWH
AI04651
tWHAX
tWHQX
Note: Clock Output Enable (GC) = Low
12/26
M440T1MV
Figure 13. Clock WRITE Mode AC Waveforms, Chip Enable-Controlled
tAVAV A0-A5 VALID tAVEH tAVEL EC tAVWL WC tWHDX DQC0-DQC7 DATA INPUT tDVWH
AI04652
tELEH
tEHAX
Note: Clock Output Enable (GC) = High
Table 5. Memory/Clock WRITE Mode AC Characteristics
M440T1MV Symbol Parameter(1) Memory -85 Min tWC tAW tWP tCEW tWR tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable Low WRITE Enable Pulse Width Chip Enable Low to Chip Enable High WRITE Enable High to Address Transition Chip Enable High to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable High WRITE Enable High to Input Transition Chip Enable High to Input Transition 85 0 0 60 65 0 15 35 35 0 15 30 70 70 5 150 150 5 Max Min 150 0 0 100 150 10 10 50 50 0 0 50 Clock Unit -15 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tDS
tDH tWEZ
tWLQZ(2,3) WRITE Enable Low to Output Hi-Z tAVWH tAVEH Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable High to Output Transition
tOEW
tWHQX(3)
Note: 1. Valid for Ambient Operating Temperature: TA = -15 to 75C; VCC = 3.0 to 3.6V (except where noted). 2. CL = 5pF. 3. If E1 - E4 and EC goes low simultaneously with W1 - W4 and WC going low, the outputs remain in the high impedance state.
13/26
M440T1MV
CLOCK OPERATION
Clock Registers Registers 00h, 01h, 02h, 04h, 06h, 08h, 09h, and 0Ah contain the time of day data in BCD. Eleven bits within these eight registers are not used and will always read '0' regardless of how they are written. Bits 6 and 7 in the Months Register (09h) are binary bits. When set to logic '0,' EOSC (Bit 7) enables the Real Time Clock oscillator. This bit will normally be turned on by the user during device initialization. However, the oscillator can be turned on and off as necessary by setting this bit to the appropriate level. Bit 6 of the Hours Register is defined as the 12- or 24-hour select bit. When set to logic '1,' the 12-hour format is selected. In the 12hour format, Bit 5 is the AM/PM bit with logic '1' being PM. In the 24-hour mode, Bit 5 is the second 10-hour bit (20-23 hours). The Clock Registers are updated every 0.01 seconds from the Real Time Clock, except when the TE Bit (Bit 7 of Register 0Bh) is set low or the clock oscillator is not running. Reading and Setting the Clock The preferred method of synchronizing data access to and from the TIMEKEEPER(R) is to access the Command Register by doing a WRITE cycle to address location 0Bh and setting TE Bit (Transfer Enable Bit) to a logic '0.' This will freeze the External Clock Registers at the present recorded time, allowing access to occur without danger of simultaneous update. When the clock registers have been read or written, a second WRITE cycle to location 0Bh and setting the TE Bit to a logic '1' will put the Clock Registers back to being updated every 0.01 second. No time is lost in the Real Time Clock because the internal copy of the Clock Register buffers is continually incremented while the external memory registers are frozen. An alternate method of reading and writing the Clock Registers is to ignore synchronization. However, any single READ may give erroneous data as the Real Time Clock may be in the process of updating the external memory registers as data is being read. The internal copies of seconds through years are incremented, and the time of day alarm is checked during the period that hundreds of seconds reads "99" to "00." A way of making sure data is valid is to do multiple READs and compare. Writing the registers can also produce erroneous results for the same reasons. A way of making sure that the WRITE cycle has caused proper update is to do a READ to verify and re-execute the WRITE cycle if data is not correct. While the possibility of erroneous results from READ and WRITE cycles has been stated, it is worth noting that the probability of an incorrect result is kept to a minimum due to the redundant structure of the TIMEKEEPER. Clock Alarm Registers Registers 03h, 05h, and 07h contain the Clock Alarm Registers. Bits 3, 4, 5, and 6 of Register 07h will always read '0' regardless of how they are written. Bit 7 of Registers 03h, 05h, and 07h are mask bits (see Table 6., page 15). When all of the mask bits are logic '0,' a Clock Alarm will only occur when Registers 02h, 04h, and 06h match the values stored in Registers 03h, 05h, and 07h. An alarm will be generated every day when Bit 7 of Register 07h is set to a logic '1.' Similarly, an alarm is generated every hour when Bit 7 of Registers 07h and 05h is set to a logic '1.' When Bit 7 of Registers 07h, 05h, and 03h is set to a logic '1,' an alarm will occur every minute when Register 1 (seconds) rolls from "59" to "00." Clock Alarm Registers are written and read in the same format as the Clock Registers. The Clock Alarm Flag and Interrupt are always cleared when alarm Registers are read or written. Watchdog Alarm Registers Registers 0Ch and 0Dh contain the time for the watchdog alarm. The two registers contain a time count from 00.01 to 99.99 seconds in BCD. The value written into the Watchdog Alarm Registers can be written or read in any order. Any access to Register 0Ch or 0Dh will cause the watchdog alarm to re-initialize and clears the Watchdog Flag Bit and the Watchdog Interrupt Output. When a new value is entered or the Watchdog Registers are read, the watchdog timer will start counting down from the entered value to zero. When zero is reached, the Watchdog Interrupt Output will go to the active state. The watchdog timer countdown is interrupted and re-initialized back to the entered value every time either of the registers are accessed. In this manner, controlled periodic accesses to the watchdog timer can prevent the watchdog alarm from going to an active level. If access does not occur, the countdown alarm will be repetitive. The Watchdog Alarm Registers always read the entered value. The actual countdown register is internal and is not readable. Writing registers 0Ch and 0Dh to '0' will disable the watchdog alarm feature.
14/26
M440T1MV
Table 6. Register Map
ADDRESS 0 BIT 7 0.1 SECONDS 0.01 SECONDS BIT 0 RANGE 00-99
1
0
10 SECONDS
SECONDS
00-59
2
0
10 MINUTES
MINUTES
00-59
3
M
10 MIN ALARM 10 10
MIN ALARM
00-59 01-12+A/P 00-23 01-12+A/P 00-23 01-07
4 CLOCK CALENDAR/ TIME OF DAY ALARM REGISTERS
0
12/24
A/P
HR
HOURS
5
M
12/24
10
A/P 0
10
HR 0
HOURS ALARM
6
0
0
0
DAYS
7
M
0
0
0
0
DAY ALARM
01-07
8
0
0
10DATE
DATE
01-31
9
EOSC
ESQW
0
10MO
MONTHS
01-12
A COMMAND REGISTER
10YEARS IBH LO PU LVL
YEARS
00-99
B
TE
IPSW
WAM
TDM
WAF
TDF
WATCHDOG ALARM REGISTERS
C
0.1 SECONDS
0.01 SECONDS
00-99
D
10 SECONDS
SECONDS
00-99
USER REGISTERS
E - 3F
SRAM ADDRESS SPACE
AI04208
Table 7. Time of Day Alarm Mask Bits
Register (03h) Minutes 1 0 0 0 (05h) Hours 1 1 0 0 (07h) Days 1 1 1 0 Alarm once per minute Alarm when minutes match Alarm when hours and minutes match Alarm when hours, minutes, and days match
Note: Any other bit combinations of mask bit settings produce an illegal operation.
15/26
M440T1MV
Command Register Address location 0Bh is the Command Register where mask bits, control bits, and flag bits reside. The operation of each bit is as follows: TE - Bit 7 Transfer Enable. This bit, when set to logic '0,' will disable the transfer of data between internal and external clock registers. The contents in the external clock registers are now frozen and READs or WRITEs will not be affected with updates. This bit must be set to a logic '1' to allow updates. IPSW - Bit 6 Interrupt Switch. When set to a logic '1,' IRQ/(IRQ) is the Watchdog Alarm. When set to a logic '0,' IRQ/(IRQ) is the time of day alarm output. IBH/LO - Bit 5 IRQ Sink or Source Current. When this bit is set to a logic '1' and VCC is applied, IRQ/(IRQ) will source current (see Table 11., page 19, IOH). When this bit is set to a logic '0,' IRQ will sink current (see Table 11., page 19, IOL). PU/LVL - Bit 4 Interrupt Pulse Mode or Level Mode. This bit determines whether the interrupt will output a pulse or level signal. When set to a logic '0,' IRQ/(IRQ) will be in the level mode. When this bit is set to a logic '1,' the pulse mode is selected. IRQ/(IRQ) will either sink or source current, depending on the condition of Bit 5, for a minimum of 3ms and then release. IRQ will only source current when there is voltage present on VCC. WAM - Bit 3 Watchdog Alarm Mask. When this bit is set to a logic '0,' the watchdog interrupt output will be activated. The activated state is determined by bits 1, 4, 5, and 6 of the Command Register. when this bit is set to a logic '1,' the watchdog interrupt output is deactivated. TDM - Bit 2 Time of Day Alarm Mask. When this bit is set to a logic '0,' the time of day alarm interrupt output will be activated. The activated state is determined by bits 0, 4, 5, and 6 of the Command Register. When this bit is set to a logic '1,' the time of day alarm interrupt output is deactivated. WAF - Bit 1 Watchdog Alarm Flag. This bit is set to a logic '1' when a watchdog alarm interrupt occurs. This bit is "Read only." The bit is reset when any of the watchdog alarm registers are accessed. When the interrupt is in the pulse mode (see PU/ LVL - Bit 4 Interrupt Pulse Mode or Level Mode), this flag will be in the logic '1' state only during the time the interrupt is active. TDF - Bit 0 Time of Day Flag. This is a "Read only" bit. This bit is set to a logic '1' when a time of day alarm has occurred. the time the alarm occurred can be determined by reading the time of
day alarm registers. This bit is reset to a logic '0' state when any of the time of day registers are accessed. When the interrupt is in the pulse mode (see PU/ LVL - Bit 4 Interrupt Pulse Mode or Level Mode), this flag will be in the logic '1' state only during the time the interrupt is active. Battery Low The M440T1MV automatically performs battery voltage monitoring upon power-up, and at factoryprogrammed time intervals of at least 24 hours. The Battery Low (BL) signal will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL signal will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval (see application note, "AN1540, NVRAM PBGA Dual Battery Hat Mounting and Removal" for more information). If a battery low is generated during a power-up sequence, this indicates that one of the batteries is below 2.5V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect, and verified as correct. Fresh batteries should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the batteries should be replaced. The SNAPHAT(R) top should be replaced with valid VCC applied to the device. The M440T1MV only monitors the batteries when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. The BL signal is an open drain output and an appropriate pull-up resistor should be chosen to control the rise time. Sleep Mode Forcing the sleep pad more positive than +7.5V above ground will cause the batteries to be isolated from the RAM, preserving the remaining battery life. This mode may be used when device operation is not necessary for an extended period of time. Note: Implementation of this Sleep Mode will result in complete loss of data.
16/26
M440T1MV
MAXIMUM RATINGS
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 8. Absolute Maximum Ratings
Symbol TA TSTG TSLD VCC VIO IO PD Parameter Operating Temperature Storage Temperature (VCC, Oscillator Off) Lead Solder Temperature for 10 seconds Supply Voltage (on any pin relative to Ground) Input or Output Voltages Output Current Power Dissipation Value -15 to 75 -40 to 85 260 -0.3 to + 4.6 -0.3 to VCC + 0.3 20 1 Unit C C C V V mA W
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
CAUTION! Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up Mode
17/26
M440T1MV
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the MeasureTable 9. DC and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
M440T1MV 3.0 to 3.6V -15 to 75C 30pF 5ns 0 to 3V 1.5V
Figure 14. AC Testing Load Circuit
DEVICE UNDER TEST
645
CL = 30 pF
1.75V
AI05605
Table 10. Capacitance
Symbol Parameter(1,2) A0 - A5 CIN Input Capacitance A6 - A19, G All Other Inputs COUT(3) CIO(3) Output Capacitance (BL) Input / Output Capacitance M440T1MV Unit Min Max 50 40 10 10 10 pF pF pF pF pF
Note: 1. Effective capacitance measured with power supply at 3V; sampled only; not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs were deselected.
18/26
M440T1MV
Table 11. DC Characteristics
Sym ILI ILO ICC1 ICC2 ICC3 VIL(2) VIH(2) VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (TTL Standby) VCC Power Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage (Open drain)(3) Output High Voltage IOL = 2.0mA IOL = 10mA IOH = -1.0mA 2.2 2.80 2.5 2.97 E1 - E4, EC = VIH E1 - E4, EC = VCCI - 0.2 -0.3 2.2 5 2 Test Condition(1) 0V VIN VCC 0V VOUT VCC M440T1MV Unit Min Typ Max 4 4 210 12 3 0.6 VCC + 0.3 0.4 0.4 A A mA mA mA V V V V V V V
VPFD(2) Power Fail Deselect VSO(2) Battery Back-up Switchover
Note: 1. Valid for Ambient Operating Temperature: TA = -15 to 75C; VCC = 3.0 to 3.6V (except where noted). 2. All voltages are referenced to Ground. 3. For BL and IRQ (Open drain); if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0V when VCC = 0V (during battery back-up mode).
19/26
M440T1MV
Data Retention Mode Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all inputs are treated as "Don't care." Note: A power failure during a WRITE cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M440T1MV may respond to transient noise spikes on VCC that cross into the deselect window during the time the device is sampling VCC.Therefore, decoupling of the Figure 15. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO VSS
power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the clock. The internal energy source will maintain data in the M440T1MV for an accumulated period of 5 years at 45C. As system power rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus tER (min). Normal RAM operation can resume tER after VCC exceeds VPFD (max). Refer to Application Note (AN1012) on the ST Web Site for more information on battery life.
tF tFB
tDR tRB DON'T CARE
tR tREC
RECOGNIZED
INPUTS
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
AI04792
Table 12. Power Down/Up Trip Points DC Characteristics
Symbol VPFD VSO tDR(3) Parameter(1,2) Power-fail Deselect Voltage Battery Back-up Switchover Voltage Expected Data Retention Time 5 M440T1MV Unit Min 2.8 Typ 2.9 2.5 Max 2.97 V V YEARS
Note: 1. Valid for Ambient Operating Temperature: TA = -15 to 75C; VCC = 3.0 to 3.6V (except where noted). 2. All voltages referenced to VSS. 3. At 45C, VCC = 0V.
20/26
M440T1MV
Table 13. Power Down/Up AC Characteristics
Symbol tF(2) tFB(3) tR tRB tREC Parameter(1) VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time Power-up Deselect Time Min 300 10 10 1 40 200 Max Unit s s s s ms
Note: 1. Valid for Ambient Operating Temperature: TA = -15 to 75C; VCC = 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
21/26
M440T1MV
PACKAGE MECHANICAL INFORMATION
Figure 16. PBGA-ZA - 168-ball Plastic Ball Grid Array Package Outline
A3
A
E
B
A A1 A2
HE
DB
B
45
GE FD
B3 B2 B1 TOP VIEW
GD
ddd C
SIDE VIEW e Non-plated thru holes
E5
1
BALL 1 CORNER
D3 b D D1
eee S C A S B S fff S C b
D2 e
SOLDER BALL (Typ) DETAIL A Fiducial and Soldermask opening (3X)
e E4
Detail A
E1 E2 E3 E BOTTOM VIEW
FE
0.20 (4X)
PBGA-Z04
Note: Drawing is not to scale.
22/26
M440T1MV
Table 14. PBGA-ZA - 168-ball Plastic Ball Grid Array Package Mechanical Data
mm Symb Typ A A1 A2 A3 B B1 B2 B3 b D D1 D2 D3 e E E1 E2 E3 E4 E5 FD FE GD GE HE n 11.64 6.60 1.50 9.25 44.40 36.60 28.25 23.10 0.76 44.50 27.94 40.00 20.56 1.27 44.50 22.86 28.40 40.00 15.75 14.38 8.28 10.82 0.85 1.00 1.32 1.12 168 Tolerance ddd eee fff 0.15 0.25 0.10 1.52 39.80 15.65 14.28 8.08 10.72 0.65 40.20 15.85 14.48 8.48 10.92 1.05 44.30 44.70 39.80 20.46 40.20 20.66 Min 11.24 6.30 1.40 9.00 44.30 36.50 28.15 23.00 0.71 44.30 Max 12.04 6.90 1.60 9.50 44.50 36.70 28.35 23.20 0.81 44.70 Typ 0.458 0.260 0.059 0.364 1.748 1.441 1.112 0.909 0.030 1.752 1.100 1.575 0.809 0.050 1.752 0.900 1.118 1.575 0.620 0.566 0.326 0.426 0.033 0.039 0.052 0.044 168 Tolerance 0.006 0.010 0.004 0.060 1.567 0.616 0.562 0.318 0.422 0.026 1.583 0.624 0.570 0.334 0.430 0.041 1.744 1.760 1.567 0.806 1.583 0.813 Min 0.443 0.248 0.055 0.354 1.744 1.437 1.108 0.906 0.028 1.744 Max 0.474 0.272 0.063 0.374 1.752 1.445 1.116 0.913 0.032 1.760 inches
23/26
M440T1MV
PART NUMBERING
Table 15. Ordering Information Scheme
Example: M440T 1MV -15 ZA 9
Device Type M440T
Supply Voltage and Write Protect Voltage 1MV = VCC = 3.0 to 3.6V; VPFD = 2.8 to 2.97V
Speed -15 = 150ns
Package(1) ZA = 168-ball Ball Grid Array
Temperature Range 9 = -15 to 75 C
Note: 1. Where "Z" is the symbol for PBGA packages and "A" denotes 1.27mm ball pitch
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
24/26
M440T1MV
REVISION HISTORY
Table 16. Document Revision History
Date September 2002 16-Jan-03 31-Mar-03 11-Apr-03 05-Oct-04 Version 1.0 1.1 1.2 2.0 3.0 First issue Modify mechanical data (Table 14) Update test condition (Table 12) Updated with template v2.2 Reformatted; update mechanical dimensions (Figure 16; Table 14) Revision Details
25/26
M440T1MV
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
26/26

▲Up To Search▲

Price & Availability of M440T1MV-15ZA9

	To Download M440T1MV-15ZA9 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .